With increasing popularity of electronic devices, such as laptop computers, portable digital assistants, digital cameras, mobile phones, digital audio players, video game consoles and the like, demand for nonvolatile memories are on the rise. Nonvolatile memories come in various types, including flash memories. Flash memories are widely used nowadays for fast information storage in electronic devices such as those mentioned above.
In flash memories, data bits are stored in an array of individual memory cells, each of which includes a floating gate transistor. Generally speaking, each of the memory cells in a flash memory looks similar to a standard metal-oxide-semiconductor field-effect transistor (MOSFET), except that a flash memory cell has two gates instead of just one. One gate, the control gate, is analogous to the gate in a MOSFET. The other gate, the floating gate, is insulated all around by an oxide layer and is between the control gate and the substrate. Because the floating gate is insulated by its insulating oxide layer, any electrons placed on it get trapped there and thereby enable the storage of data. More specifically, when electrons are on the floating gate, their presence modifies, by partially canceling out, the electric field coming from the control gate. This results in the modification of the threshold voltage of the transistor, since a higher electric field is now required to enable an electrical current to flow between the source and the drain of the transistor than it would require without the electrons on the floating gate. If the number of electrons on the floating gate is sufficiently large, the resulting modified threshold voltage will be so high as to inhibit any electrical current to flow between the source and the drain when the normal operating voltage is applied to the control gate. Hence, in a typical flash memory cell that stores a binary bit, electrical current will either flow or not flow when a memory cell is being read by applying a voltage on the control gate, depending on the number of electrons on the floating gate. The flow or no flow of electrical current, in turn, translates to a binary bit 1 or 0, respectively.
In the pursuit of greater storage capacity in yet smaller chips, the flash memory density has been increasing over the years in accordance to the Moore's Law, largely due to the down scaling of the memory cell dimensions. The continued down scaling of MOS devices has created many challenges and opportunities, among them the formidable requirement for an ultra-thin gate oxide. One serious problem that comes along with thin oxide, and hinders further down scaling, is excessive leakage current. Specifically, when the oxide layer surrounding the floating gate of a flash memory cell is so thin that electrons stored on the floating gate may leak out (e.g., from the floating gate to the control gate and the word line that is coupled to the control gate, and eventually to ground), a result is that a binary bit 0 originally stored in the memory cell might now appear to be a binary bit 1.
Since the excessive leakage current for such an ultra-thin oxide will be unacceptable for very-large-scale integration (VLSI) applications, it is imperative that flash memories with unacceptable leakage current be identified during manufacturing process. As such, during manufacturing, flash memories are tested to assure that they are operating properly (e.g., having allowable leakage current). A leakage test is conducted to measure the leakage current on the word lines of each flash memory to determine whether the leakage current on any of the word lines is excessive and thus unacceptable.
Conventionally, the leakage current in memory devices is measured using external leakage measurement instrument during the manufacturing process. FIG. 1A illustrates a conventional leakage measurement system 100 showing how the leakage current in a memory device, such as a flash memory, is measured. An external leakage measurement instrument 120 is connected to a conventional memory device 110 via pad 130, which is connected to rows decoder 140 in the memory device 110. The rows decoder 140 is coupled to the word lines of the memory device (not shown). The external leakage measurement instrument 120 selects the word line on which the value of leakage current is measured by sending a selection signal to rows decoder 140, which in turn selects the word line.
FIG. 1B illustrates a conventional leakage measurement system 105 for measuring the leakage current on one of the word lines of the conventional memory device 110 of FIG. 1A. As shown, word line 150 is selected for leakage current measurement and is coupled to the external leakage measurement instrument 120 via pad 130 and rows decoder 140. Leakage paths of leakage current on a given word line may exist, for example, between a word line and another word line. One way to measure the leakage current on a given word line is to place on the word line a voltage that is different from the voltage on neighboring word lines. As a result, the voltage differential would induce leakage current to flow and thereby be detected and measured. Referring to FIG. 1B, when word line 150 is at voltage Vcc and its neighboring word line 160 is at 0 volt, a leakage current 170 may flow from word line 150 to word line 160, and is measured by the external leakage measurement instrument 120.
However, this kind of leakage measurement takes longer time than ideal since leakage current is measured from outside of the memory devices. This results in long test time and leads to long manufacturing cycle, which translates into high cost of production. There is therefore a need for a way to reduce the test time required to measure leakage current on the word lines of memory devices such as flash memories.